The present invention relates to a device (to be referred to as a D/A converter hereinafter) for converting a digital signal into an analog signal and, more particularly, to a local D/A converter applied to an oversampling type D/A converter.
In some D/A converters, an original digital signal is interpolated in an input digital signal at the timing of a clock having a transfer rate 10 or more times higher than that of the input digital signal, and the interpolated signal undergoes digital filtering. Thereafter, a 1-bit digital signal obtained by pulse-density modulation of the original signal is output from a .DELTA..SIGMA. (delta/sigma) modulator. A D/A converter using such a scheme is called an oversampling type D/A converter (refer to, e.g., NIKKEI ELECTRONICS, August 1988, No. 453, p. 220, and Technical Report, The Institute of Electronics, Information and Communication Engineers, ICD91-88, August 1988).
According to this scheme, since the proportion of an analog circuit to the overall device is low, and a weighting scheme using capacitors and resistors is not used, a high-precision D/A converter can be realized.
FIG. 6 shows an oversampling type D/A converter. A digital signal 31 is input to an interpolation filter 61 at the timing of a clock signal 32. Digital data is then interpolated in the digital signal 31 at the period of an oversample clock signal 34. The signal is then filtered by a digital low-pass filter 62. The resultant signal is then input to a secondary .DELTA..SIGMA. modulator 71. The .DELTA..SIGMA. modulator 71 is constituted by two digital integrators 64 and 66, digital subtracters 63 and 65, and a quantizer 67. If an input to the .DELTA..SIGMA. modulator 71 is represented by X; an output from the .DELTA..SIGMA. modulator 71, by Y; and quantization noise, by Q, the following equation (1) is established: EQU Y=X+(1+Z.sup.-1).sup.2 .multidot.Q (1)
A 1-bit digital signal 37 obtained by pulse-density modulation of the digital signal 31, i.e., an output from the quantizer 67 which is an output from the .DELTA..SIGMA. modulator 71, is input to a local D/A converter 72 in synchronism with the oversample clock signal 34. The local D/A converter 72 is constituted by a 1-bit D/A converter 68 and a low-pass filter 69. When the output from the quantizer 67 is converted into an analog signal by the 1-bit D/A converter 68, and the analog signal is filtered by the low-pass filter 69, a high-precision analog signal 33 can be obtained.
FIGS. 7A to 7F show operations of the respective portions of the circuit shown in FIG. 6. As shown in FIG. 7C, data is inserted in the digital signal 31 in FIG. 7A, at a period f.sub..PHI.S of the oversample clock signal 34 in FIG. 7F, by the interpolation filter 61, which receives the clock signal 32 shown in FIG. 7B, thereby obtaining an output 35. FIG. 7C exemplifies the case wherein zero data is inserted. In addition, an output 36 shown in FIG. 7D is obtained according to the characteristics of the digital low-pass filter 62. As indicated by equation (1), the input signal X (output 37) is directly obtained, as the output signal Y in shown in FIG. 7E, by the secondary .DELTA..SIGMA. modulator 71, except for quantization noise which is concentrated in a high-frequency range. That is, the data of the output 36 is equivalent to that of the output 35. In other words, the data of the output 37 is obtained by pulse-density modulation of the data of the output 36.
The example of an oversampling type D/A converter has been described above. Since the precision of a D/A converter of this scheme is greatly dependent on the precision of a local D/A converter, the local D/A converter has a full differential arrangement.
FIG. 8 shows a conventional example of the local D/A converter 72 in FIG. 6. Referring to FIG. 8, the local D/A converter has the following circuit arrangement. A switch S1 is arranged between the first electrode of a capacitor 13 and a reference voltage source 7; a switch S2, between the first electrode of the capacitor 13 and a reference voltage source 8; and a switch S4, between the first electrode of the capacitor 13 and a reference voltage source 9. A switch S1 is arranged between the first electrode of a capacitor 14 and the reference voltage source 8; a switch S2, between the first electrode of the capacitor 14 and the reference voltage source 7; and a switch S4, between the first electrode of the capacitor 14 and the reference voltage source 9. A switch S3 is arranged between the second electrode of the capacitor 13 and the reference voltage source 9; and a switch S4, between the second electrode of the capacitor 13 and the inverting input of a full differential type operational amplifier 17. A switch S3 is arranged between the second electrode of the capacitor 14 and the reference voltage source 9; and a switch S4, between the second electrode of the capacitor 14 and the noninverting input of the full differential type operational amplifier 17. The inverting input and noninverting output of the full differential type operational amplifier 17 are connected to each other through a capacitor 15, while a switch S3 is arranged between the inverting input and the noninverting input. The noninverting input and inverting output of the full differential type operational amplifier 17 are connected to each other through a capacitor 16, while a switch S3 is arranged between the noninverting input and the inverting output. The noninverting and inverting outputs of the full differential type operational amplifier 17 are respectively connected to the first and second inputs of a full differential type low-pass filter 10. The first and second outputs of the full differential type low-pass filter 10 are respectively connected to analog signal output terminals 11 and 12. The reference voltage sources 7, 8, and 9 are respectively set at voltages Vr.sup.-, Vr.sup.+, and Vag. The output 37 from the .DELTA..SIGMA. modulator 71 is input to an input terminal 19, i.e., the first input of a decoder 18. The oversample clock signal 34 is input to an input terminal 20, i.e., the second input of the decoder 18. Outputs .PHI.1, .PHI.2, .PHI.3, and .PHI.4 from the decoder 18 serve to control the switches S1, the switches S2, the switches S3, and the switches S4, respectively.
FIGS. 9A to 9G show operations of the respective portions of the circuit in FIG. 8. When a pulse-density-modulated output 37 (FIG. 9A) from the .DELTA..SIGMA. modulator 71 is input to the input terminal 19 of the decoder 18 constituting the local D/A converter 72, and an oversample clock signal 34 shown in FIG. 9B is input to the input terminal 20 of the decoder 18, the outputs .PHI.1, .PHI.2, .PHI.3, and .PHI.4 are decoded at the respective timings shown in FIGS. 9C to 9F, thus ON/OFF-controlling the switches S1, S2, S3, and S4, respectively. With this operation, as shown in FIG. 9G, a differential voltage 113 is generated between a noninverting output 111 and an inverting output 112 of the full differential type operational amplifier 17. If, for example, the difference voltage 113 (Vr.sup.+ -Vr.sup.-) is represented by Vp; and a difference voltage (Vr.sup.- -Vr.sup.+), by Vm, the difference voltage Vp is obtained when the output 37, as a digital signal, from the .DELTA..SIGMA. modulator 71 is at logic "1", whereas the difference voltage Vm is obtained when the output 37 is at logic "0". That is, digital signals of logic "1" and logic "0" are converted into analog signals Vp and Vm. These analog signals are then filtered by the full differential type low-pass filter 10. The resultant signals are obtained, as full differential analog signals of higher precision, from the analog signal output terminals 11 and 12.
In this conventional local D/A converter, since a digital signal is converted into an analog signal by using a full differential type operational amplifier, the speed of local D/A conversion is limited by the infinite GB product of the operational amplifier. More specifically, the limit frequency of D/A conversion based on the infinite GB product of the full differential type operational amplifier is generally set to be several tens of MHz. In addition, in order to increase the speed of D/A conversion, the GB product of the full differential type operational amplifier must be increased. As a result, the power consumption and the circuit size are increased.